Mark Litterick proposed an important rule for designing reliable Clock Domain Crossing (CDC) systems using a two-flip-flop synchronizer.

When transferring a CDC signal between two clock domains,
the signal must remain stable for at least 1.5× (one and a half times) the period of the receiving clock.

Litterick summarized this as:

“Input data values must be stable for three destination clock edges.”

⚙️ What This Means

For a CDC transfer to work reliably:

• The asynchronous input signal should not change too quickly relative to the receiving clock.
• It must stay constant for at least the time it takes for three edges of the receiving clock to occur:
  • The first edge samples the input into the first flip-flop.
  • The second edge allows metastability to decay.
  • The third edge ensures a stable output at the synchronizer’s second stage.

If the signal changes earlier, the synchronizer might not have enough time to resolve metastability, risking incorrect or unstable outputs.

📉 Relaxing the Requirement

For systems with very long clock periods (i.e., low-frequency designs):

• The requirement can sometimes be relaxed to about 1.25× the destination clock period.
• However, the “three edge” rule remains the safest design guideline —
  it provides a robust margin and is easier to verify through SystemVerilog assertions.

🔁 Applicability

The three-edge rule applies to both open-loop and closed-loop synchronization methods:

• Closed-loop synchronizers (e.g., handshaking circuits) inherently ensure this condition is met,
  as they wait for acknowledgment signals before changing the input again.
• Open-loop synchronizers rely on the designer to ensure signal stability for the required duration.

✅ Design Takeaway

• Keep CDC input signals stable for at least three edges of the destination clock.
• This guarantees adequate metastability resolution time and ensures reliable synchronization.
• When in doubt — design conservatively and follow the three-edge guideline.